/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2021-2023. All rights reserved.
 * Description: UDK memory barrier for ARM architecture header file
 * Author: -
 * Create: 2021.4.20
 */

#ifndef UDK_MEMBARRIER_ARM_H
#define UDK_MEMBARRIER_ARM_H

/*
 * Prefetch specific memory to all cache include L0 cache.
 */
static inline void udk_prefetch0(const volatile void *p)
{
    asm volatile("PRFM PLDL1KEEP, [%0]" : : "r"(p));
}

/*
 * Insert a hardware memory barrier to ensure no out-of-order write operations.
 */
#define udk_wmb() asm volatile("dmb oshst" : : : "memory")

/*
 * Insert a hardware memory barrier to ensure no out-of-order read operations.
 */
#define udk_rmb() asm volatile("dmb oshld" : : : "memory")

/*
 * Insert a hardware memory barrier to protect both read and write operations.
 */
#define udk_mb() asm volatile("dmb osh" : : : "memory")

/*
 * Write memory Barriers for multiprocessors.
 */
#define udk_smp_wmb() asm volatile("dmb ishst" : : : "memory")

/*
 * Read memory Barriers for multipocessors.
 */
#define udk_smp_rmb() asm volatile("dmb ishld" : : : "memory")

/*
 * Memory Barriers for multipocessors.
 */
#define udk_smp_mb() asm volatile("dmb ish" : : : "memory")

#endif /* UDK_MEMBARRIER_ARM_H */